1. Field of the Invention
This invention relates to an oscillator and more particularly to an oscillator that is insensitive to power supply ripple.
2. Description of the Related Art
In conventional phase-locked loops (PLLs) when high-supply ripple immunity is required typically more than one level of regulation is employed. As a consequence, the PLL operates from high-supply voltages (typically 2.5V to 3.3V range) and therefore increases power dissipation. Conversely, when high-supply voltage is not readily available, in presence of supply ripple, the PLL output clock spectrum will not be clean and contain spurs (or equivalently, the time domain clock waveform will have supply-induced jitter). The voltage controlled oscillator (VCO) block in the PLL may be particularly sensitive to supply ripple.
FIG. 1 illustrates a conventional PLL. An input signal having a frequency fin is supplied to an input divider 101. The output of the input divider 101 is supplied to the phase/frequency detector (PFD) 103 that compares the divided down input signal to a feedback signal from a feedback divider 105. The output of the PFD is used to adjust the charge pump output current pulse width 107, which supplies the VCO whose output frequency is tuned according to the charge pump output.
In order to reduce supply ripple induced spurs, various regulation schemes are used. In one scheme, referring to FIG. 2, only a single regulator 201 is used for the entire PLL 100. At the other extreme, as shown in FIG. 3, every PLL block has its own dedicated regulator. In large mixed-signal chips where there is a large noisy digital section, it is difficult to keep the PLL supply clean. External switching regulators, e.g., DC-DC converters, can also contribute significantly to the supply ripple. FIG. 4 depicts the output clock spectrum of a PLL with frequency f0 for a sinusoidal supply ripple at frequency fripple. As shown in FIG. 5, regulating the supply voltage with regulator 501 reduces the VCO output spurs as compared to the unregulated case shown in FIG. 4.
In some cases where spur requirements are stringent, more than one level of regulation is needed as illustrated in FIG. 6. In such a case, due to regulator head-room requirements, the supply voltage needs to be increased. The first regulator 601 supplies an intermediate supply voltage (vreg1) of, e.g., 1.8V to 2.5V. The second regulator 603 supplies a supply voltage (vreg2) of 1.2V for use by the PLL 605. However, increasing the supply voltage leads to wasted power consumption, as other circuits in the system may also be connected to the supply voltage.
The above described deficiencies of conventional PLLs are merely intended to provide an overview of some of the problems of current technology and are not intended to be exhaustive. Other problems with the state of the art and corresponding benefits of various embodiments described herein may become further apparent upon review of the following detailed description.